(1) Field of the Invention
The present invention relates to an information processing apparatus in which data is written/read to/from a memory, especially to an information processing apparatus in which the same signal lines are shared for transmitting address signals, data signals and control signals.
(2) Description of the Related Art
A Synchronous Dynamic Random Access Memory (SDRAM) is used for a main storage device in home audio-video equipments such as personal computers and digital televisions.
A CPU included in home audio-video equipments has a cache memory that achieves a higher transfer rate than an SDRAM. A CPU reads data from an SDRAM, and stores the read data in a cache memory before using it.
Here, when a cache memory requests data from an SDRAM, it additionally reads data distributed near the requested data from the SDRAM, and stores therein the additionally read data. Thus, there is a higher chance that data that will be demanded after the request is also stored in the cache memory. (see Non-Patent Document 1)
The requested data and the additionally read data collectively form a block.
An SDRAM allows addresses of wraparound to enable data reading to be performed in units of a block.
Home audio-video equipments also include an LSI, which functions as a memory control unit. An LSI controls an SDRAM by means of data buses for transmitting data signals, address buses for transmitting address signals, and control buses for transmitting control signals (CLK, RAS, CAS, CS, WE, CKE, and DQM)
The number of data buses and the number of address buses respectively increase in proportion to the bits of data to be written/read to/from an SDRAM and the bits of an address.
Recent development of larger capacity memories causes the bits of data and the bits of an address to increase, thereby increasing the number of data buses and the number of address buses.
This poses the following problem. More buses requires more terminals in an LSI to transfer data and addresses, to increase the size of the package of an LSI. As a result, the manufacturing cost of an LSI is increased.
To solve the above-mentioned problem, an information processing apparatus in which an SDRAM is controlled by sharing a same bus which functions as a data bus, an address bus and the like has been developed. (see Patent Document 1)
However, the information processing apparatus sharing a same bus disclosed in JP2000-267985 can not make use of a wraparound function of an SDRAM. Accordingly, the information processing apparatus cannot perform information processing with maintaining consistency between data stored in a cache memory and data stored in an SDRAM.
In light of the above problem, the object of the present invention is to provide a useful information processing apparatus which has a memory control unit with a smaller number of terminals for signal input/output and in which information processing is performed with maintaining consistency between data stored in a cache memory and data stored in a memory unit.
Patent Document 1: unexamined Japanese patent application publication 2000-267985
Non-Patent Document 1: How Microprocessors Work (Irasuto de yomu microprocessor nyuumon), Gregg Wyant and Tucker Hammerstrom, Impress Corporation, 1995, pages 78–79